抽象的

Low Power High Speed Differential Current Comparator

Indrani Roy, Suman Biswas, B. S. Patro

A low power high speed differential current comparator having weak current operation has been presented in this paper. The comparator proposed is a three stage process. It utilizes a modified Wilson's current mirror circuit for current to voltage conversion for its first stage followed by differential amplifier stage and buffer stage. The current comparator is simulated using Cadence Virtuoso 0.18μm CMOS technology and it can successfully generate valid output response for a range of input frequencies. Working at a supply of 1.8V, the comparator is capable of sensing a minimum difference of 22nA for 4μA reference current. In addition power dissipation of this circuit is as low as 226μW and shows a swift response resulting in a propagation delay which is less than 0.8ns for an input difference of 1μA.