抽象的

Low Power Full Adder Circuit Implemented In Different Logic

Debika Chaudhuri, Atanu Nag, Sukanta Bose

The aim of this paper is to evaluate the performance of One-bit full adder cell. Different Full Adder cell with conventional static CMOS Adder is being compared. Each Cell showed different power consumption and Delay. Power consumption and speed are two important but conflicting design aspects; hence a better way to evaluate circuit performance is power delay product (PDP).The driving capability of a full adder is very important, because, full adders are mostly used in cascade configuration, where the output of one provides the input for other. Here, we have given a brief description of the evolution of full adder circuits in terms of lesser power consumption, higher speed and lesser chip size. Starting from the most conventional 28 transistor full adder we have gradually studied full adders consisting of as less as 14 transistors (14 T), 16 transistors (16T), CMOS Transmission Gate (TG), Complementary Pass-transistor Logic (CPL), Gate Diffusion Input (GDI) and Static Energy Recovery Full Adder (SERF) to meet the requirements