抽象的

Improved Multiplier Design for Digital Signal Processing Applications

Nishok.V.S, Shaheema.S, Dr.P.Poongodi

Multipliers play a key role in the high performance digital systems. Design considerations of multipliers include the following- high speed, low power consumption, regularity of layout and hence less area or even combination of them, making them suitable for various compact high speed, low power VLSI implementations. However area and speed are two conflicting constraints and improving speed results always in larger areas. A booth multiplier is a parallel multiplier that uses carry look ahead algorithm. A new (4:2) compressor design for Booth multiplier is proposed in order to reduce latency and improve speed. The key design point is to use an available signal, in the sum path, for carry generation. The comparison of these Architectures is carried out to know the best architecture for multiplication with respect to power and delay characteristics. The designs are implemented using Tanner and synthesis is done.