抽象的

Gate Count Comparison of Different 16-Bit Carry Select Adders

M.Lavanya

Addition is the most fundamental computational process encountered in digital system. An area efficient carry select adder is proposed in this paper by comparing the Gate count of Regular and Modified 16-bit carry select adders with a proposed Common Boolean Logic carry select adder. In this paper, Gate count evaluation of Regular, Modified and proposed designs are given in terms of INVERTER, NAND and NOR Gates. The comparison results shows that the common Boolean logic carry select adder structure require lesser number of gates than that of Regular and Modified 16-bit carry select adder.