抽象的

â??Design and Development of Scalable FFT Architecture for Filter Bank De-multiplexing Applicationâ?

MADHUSUDHAN. S, NAGENDRA KUMAR.M

This paper proposes a high speed FFT implementation based on Radix-22 single path delay feedback pipelined structure which was implemented on an FPGA. The radix-22 algorithm is used to decrease the number of non trivial multiplication. The number of multiplication needed for calculating the FFT by this algorithm is same as that of radix-4 but its butterfly structure is equivalent to that of radix-2. The simple radix-2 structure helps in efficient VLSI implementation. The single path delay feedback structure is used for the implementation of the algorithm to make it pipelined, which is a part of the filter bank architecture for satellite application.

免责声明: 此摘要通过人工智能工具翻译,尚未经过审核或验证

索引于

学术钥匙
研究圣经
引用因子
宇宙IF
参考搜索
哈姆达大学
世界科学期刊目录
学者指导
国际创新期刊影响因子(IIJIF)
国际组织研究所 (I2OR)
宇宙

查看更多