抽象的

Area and Time Efficient FFT Architecture Using Hardwired Pre-Shifted Bi-Rotation Cordic Design

Manikandan .M, Paramasivam .C

This paper presents CORDIC based feed forward FFT architecture. It is used to implement the pipeline FFT hardware architecture. The radix 2k feed forward FFT architecture can be used for the any number of parallel sample which is power of two. It can be achieved the high throughput and low hardware requirement. The hardwired pre shifted bi- rotation cordic technique for barrel-shifter of proposed circuit. Here two proposed CORDIC cells are used to the fixed angle rotations. This cells going to implement the micro rotations and scaling interleaved, it’s implemented the two stages. The cascade proposed the bi-rotation CORDIC for higher throughput and reduced latency implementation. This method proposed optimized set of micro rotations for fixed and known angles. Shift and add circuits are used to implement the scaling factor. Fixed means square error used for analysis and reduced the error in this method. Synthesized the proposed CORDIC cells by Synopsys Design Compiler using TSMC 90-NM library, and shown that the proposed designs offer higher throughput, less latency and less area-delay product than the reference CORDIC design for fixed and known angles of rotation. We find similar results of synthesis of different Xilinx field-programmable gate-array platforms.