抽象的

32-Bit CMOS Comparator Using a Zero Detector

M Premkumar, P Madhukumar

In this paper a new comparator design is proposed by using parallel prefix tree with Zero Detector as decision module. This comparator reduces the power and area requirements. When compared to normal parallel prefix tree based comparator the power is reduced by 225mw because of usage of zero detectors as the decision module. This area and power efficient structure can be used in modern CPU ALUs for improved performance. The simulation results for both parallel prefix tree alone and parallel prefix tree along with Zero detector were compared. Modelsim-Altera 10.1D has been used for simulation of comparators and their power and area analysis was derived by using Xilinx ISE 10.1.